Smart IoT Devices Using AI-Based Energy-Efficient Edge Computing Architecture
Author: Sayamuddin Ahmed Jilani, Soumitra Kumar Mandal
Pages: 1-13
DOI: https://doi.org/10.55306/CJDTES.2026.030101
Abstract:

As the number of IoT-connected smart objects, including environmental, wearable, smart-home, and industrial sensors, keeps growing, delivering low-latency, privacy-preserving intelligence at the network edge is no longer just convenient; it is becoming a requirement. Conventional edge deployments typically rely on fixed resource allocations that pay little attention to fluctuating workloads, device heterogeneity, or battery constraints, so energy ends up being spent needlessly. This paper introduces an edge computing framework built around four coordinated, energy-aware components: a reinforcement-learning (RL) task-offload scheduler, an adaptive dynamic voltage and frequency scaling (DVFS) controller, a dynamic model quantization/pruning engine, and a duty-cycled sensor gating manager. These sit within a four-tier architecture spanning the cloud, edge orchestration, edge compute, and device layers, extending the three-tier structure common in industry practice by introducing an explicit orchestration tier with clearly defined responsibilities. We describe the resulting system architecture and interlayer coordination protocol and evaluate the approach through a discrete-event simulation calibrated against representative embedded-inference power profiles. The simulated results show a 77.6% reduction in energy per inference relative to cloud-only offloading, a 57.0% reduction relative to a statically configured edge baseline, and a 3.7x improvement in projected device battery life, with end-to-end latency scaling sub-linearly as concurrent device load increases. An ablation study shows removing the RL-based offload scheduler causes the largest single drop in performance, with dynamic quantization contributing the next-largest share. We close by addressing real-world deployment challenges, particularly scale and security, and point to federated edge learning and standardized, cross-layer energy orchestration as key directions for future work.
Key Words: AEdge Computing, Internet of Things, Energy Efficiency, Reinforcement Learning, TinyML, Dynamic Voltage and Frequency Scaling, Model Quantization, Task Offloading.
Citation: S.A. Jilani et al., “Smart IoT Devices Using AI-Based Energy-Efficient Edge Computing Architecture” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 3(1), pp. 01-13, 2026, doi: 10.55306/CJDTES.2026.030101

Emerging Computing Strategies in VLSI: A Comprehensive Review of Device, Architecture, and Beyond-CMOS Paradigms
Author: Yakaiah. P, Kiran Chand Ravi
Pages: 14-34
DOI: https://doi.org/10.55306/CJDTES.2026.030102
Abstract:

Very-large-scale integration (VLSI) has progressed from few-thousand-transistor planar MOS circuits in 1970 to multi-billion-transistor heterogeneous systems approaching angstrom-scale nodes in 2025. As classical Dennard and Moore scaling have slowed, the field has diversified into a rich set of emerging computing strategies spanning device architecture (FinFET, gate-all-around nanosheet, complementary-FET), memory-centric computation (compute-in-memory using resistive, phase-change and magnetic devices), brain-inspired neuromorphic circuits, beyond-CMOS state-variable logic (spintronic, quantum-dot cellular automata, reversible/adiabatic computing), quantum-ready cryogenic CMOS, silicon-photonic computation, and heterogeneous 3-D/chiplet integration. This paper presents a critical, systematic review of 78 peer-reviewed and standards-body sources spanning 1961–2025, organized around a five-branch taxonomy of emerging VLSI computing strategies. We summarize the historical evolution of the field, describe a reproducible systematic-literature-review (SLR) methodology, derive the governing mathematical foundations and device models (MOSFET drive current, subthreshold swing, Dennard relations, dynamic power and energy-delay product, compute-in-memory Ohm's-law multiply-accumulate, leaky-integrate-and-fire neuron dynamics, and the Landauer thermodynamic limit), and present a critical, metric-based comparison across paradigms using four original comparative tables and four analytical graphs compiled from the reviewed literature. We identify open research gaps in cross-paradigm benchmarking, analogue-computation linearity and variability, non-volatile-device endurance, cryogenic co-design, and standardized energy-efficiency reporting, and we pose a set of future research questions intended to guide the next generation of VLSI computing research.
Key Words: 3-D integration, approximate computing, compute-in-memory, chiplets, CMOS scaling, cryo-CMOS, FinFET, gate-all-around, low-power design, Moore's law, neuromorphic computing, quantum computing, silicon photonics, spintronics, VLSI.
Citation: Yakaiah. P et al., “Emerging Computing Strategies in VLSI: A Comprehensive Review of Device, Architecture, and Beyond-CMOS Paradigms” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 3(1), pp. 14-34, 2026, doi: 10.55306/CJDTES.2026.030102.

Edge-Federated Neuro-Symbolic Intrusion Detection System for Zero-Day Cyber Threats
Author: Roshan. K, Manasa. K
Pages: 35-44
DOI: https://doi.org/10.55306/CJDTES.2026.030103
Abstract:

The fast-growing rate of the IoT-enabled environment, in turn, has greatly amplified the vulnerability to advanced cyber threats, in the form of the zero-day attacks that are not detected by signature-based solutions. The current intrusion detection systems (IDS) are mostly based on centralized learning and black-box model that restricts the scaling implementations, privacy and interpretability. The research gap is the most significant since there is no common framework that can guarantee decentralized learning, flexibility to unknown attacks, and elucidated decision-making. In response to this, an Edge-Federated Neuro-Symbolic Intrusion Detection System (EF-NSIDS) is suggested which combines federated learning at the edge with symbolic reasoning to detect threats in an interpretable way. The framework uses distributed edge nodes to train local models, a neuro-symbolic inference engine to extract the rules, and a global knowledge aggregation mechanism to combine the knowledge. Benchmark datasets such as CIC-IDS2017 and UNSW-NB15 are used to conduct experiments in a simulated IoT network scenario where the data distribution is that of non-IID. The proposed model attains an accuracy of 97.84, a precision of 96.92, a recall of 97.15 and F1-score of 97.03, which are higher than the models of deep learning-based IDS. The findings show that there is better zero-day detection that is more transparent and has lower communication overheads.
Key Words: AI, Edge Computing, Federated Learning, Intrusion Detection System, IoT Security, Neuro-Symbolic AI, Zero-Day Attacks.
Citation: Roshan. K et al., “Edge-Federated Neuro-Symbolic Intrusion Detection System for Zero-Day Cyber Threats” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 3(1), pp. 35-44, 2026, doi: 10.55306/CJDTES.2026.030103

A Study of the Principles and Applications of Superconducting Quantum Sensors for Microwave and Magnetic Sensing
Author: Ravindranadh Jammalamadugu
Pages: 45-53
DOI: https://doi.org/10.55306/CJDTES.2026.030104
Abstract:

Superconducting quantum sensors use flux quantization, the Josephson effect and low-loss microwave circuits to measure magnetic flux, microwave signals and photon flux close to fundamental limits. In this review we follow the field from the Bardeen–Cooper–Schrieffer theory and the discovery of Josephson tunnelling to SQUID magnetometers, microwave kinetic inductance detectors and quantum-limited parametric amplifiers. We explain how dc and rf SQUIDs, superconducting resonators, and Josephson and kinetic-inductance amplifiers work, and we describe one measurement chain that covers them all, with separate excitation, response, amplification, control and readout paths and a flux-locked-loop variant for SQUIDs. Flux and field noise, noise-equivalent power, added noise, bandwidth and dynamic range are defined and compared using numbers taken directly from the primary literature, together with the conditions under which they were measured. We then survey applications in biomagnetism, astronomical imaging, qubit readout and dark-matter searches, and close with the open problems of scalability, environmental noise and fair benchmarking.
Key Words: Josephson junctions, kinetic inductance detectors, magnetometers, parametric amplifiers, quantum limit, SQUID, superconducting sensors.
Citation: Ravindranadh J, “A Study of the Principles and Applications of Superconducting Quantum Sensors for Microwave and Magnetic Sensing” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 3(1), pp. 45-53, 2026, doi: 10.55306/CJDTES.2026.030104

Design-for-Testability Architectures for 3D Integrated Circuits with Through-Silicon Via Fault Diagnosis: A Comprehensive Review and Future Directions
Author: Ramesh Babu N, Sreenu Babu Doddavarapu
Pages: 54-76
DOI: https://doi.org/10.55306/CJDTES.2026.030105
Abstract:

Stacking dies with through-silicon vias (TSVs) shortens interconnects and raises bandwidth, but every extra stacking step brings defect mechanisms that planar test flows were never built to catch. One bad TSV can sink a stack of otherwise good dies, so test access, detection and, above all, diagnosis largely decide whether a 3D product makes money. We review peer-reviewed work from about 2010 to 2026, along with a handful of earlier foundational papers, on design for testability (DFT) in TSV-based 3D ICs and on TSV fault diagnosis. The review covers TSV structure, fabrication and electrical behavior, and it proposes a fault taxonomy that separates manufacturing, parametric, environment-induced and lifetime mechanisms. It then compares test-access architectures (including IEEE Std 1838), scan and compression, built-in self-test, contactless pre-bond methods, online testing, redundancy and thermal-aware scheduling. A separate section looks at machine-learning diagnosis: which features, models, datasets and metrics the literature actually uses. What we find is that ML results look promising but rest mostly on simulated or small experimental datasets, and few have been checked against physical failure analysis. We finish with a gap analysis, a roadmap, and specific PhD-level topics on AI-assisted DFT, thermal-aware multi-fault diagnosis, chiplet-level test and repair, reliability-aware diagnosis, digital twins and self-diagnosing stacks.
Key Words: A3D integrated circuits, built-in self-test, design for testability, fault diagnosis, machine learning, test access mechanism, thermal-aware testing, through-silicon vias.
Citation: Ramesh B N et al., “Design-for-Testability Architectures for 3D Integrated Circuits with Through-Silicon Via Fault Diagnosis: A Comprehensive Review and Future Directions” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 3(1), pp. 54-76, 2026, doi: 10.55306/CJDTES.2026.030105