A Comprehensive Framework for Perceptual Quality Assessment in AI-Based Image Compression
Author: Mahesh. Boddu, Soumitra Kumar Mandal
Pages: 63-87
DOI: https://doi.org/10.55306/CJDTES.2025.020201
Abstract:

Perceptual quality assessment has become the central bottleneck in the design, evaluation, and deployment of artificial-intelligence-based image compression systems. Classical signal-fidelity measures such as mean squared error (MSE) and peak signal-to-noise ratio (PSNR) correlate poorly with human judgment. Learned codecs, meanwhile, increasingly optimize directly for structural, perceptual, and generative objectives. How those objectives behave under the rate–distortion–perception trade-off is still not well understood. This paper presents a critical review of the field spanning 1970 to 2023, drawing on 75 peer-reviewed and archival sources selected through a PRISMA-informed screening protocol. We trace how image compression and quality assessment evolved together, from Shannon's rate-distortion theory through DCT- and wavelet-based standards to learned nonlinear transform coding and generative codecs. The mathematical foundations of rate–distortion theory, structural similarity, information fidelity, and the rate–distortion–perception function are then formalized, and a taxonomy is presented covering classical, structural, perceptual, no-reference, and AI-based quality metrics. Learned and generative compression architectures are examined in detail, hyperprior, autoregressive, transformer, and diffusion-based designs among them. Building on this synthesis, we propose a unified evaluation framework that folds pixel, structural, perceptual, semantic, and task-fidelity dimensions into a single adaptively weighted assessment protocol suited to modern AI-based codecs. The paper also catalogues the subjective datasets and protocols that underlie the field and presents comparative tables of representative metrics and codecs. It closes by identifying six research gaps, nine future research questions, and a short-, medium-, and long-term roadmap. The review is meant to serve as both a technical reference and an agenda-setting document for researchers, standards bodies, and practitioners working where learned compression meets perceptual quality science.
Key Words: image compression, perceptual quality assessment, rate–distortion–perception trade-off, learned image compression, generative compression, structural similarity, deep perceptual metrics, systematic literature review, subjective image quality, no-reference IQA.
Citation: Mahesh B et al., “A Comprehensive Framework for Perceptual Quality Assessment in AI-Based Image Compression,” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 2(2), pp.63-87, 2025, DOI: 10.55306/CJDTES.2025.020201

A Study of Quantum-Inspired Signal Processing for Future Communication Systems
Author: Balaiah Miska
Pages: 88-97
DOI: https://doi.org/10.55306/CJDTES.2025.020202
Abstract:

Networks built to sixth-generation (6G) targets will have to hold sub-millisecond latency, push spectral efficiency past what today's massive MIMO deployments achieve, and manage resources across highly heterogeneous nodes with little human supervision. Those targets place a hard demand on the optimizer. Channel estimation, adaptive modulation, beamforming and decoding all involve searching large, non-convex parameter spaces, and the search has to finish inside a coherence interval that may last only a few hundred microseconds. This paper surveys quantum-inspired signal processing (QISP), a family of classical algorithms that borrow structure from quantum computation, including amplitude-weighted superposition sampling, quantum-walk-style exploration, Ising-model formulations and tensor-network compression, but that run entirely on conventional processors. We group the literature under four headings: algorithmic foundations, communication-system architectures, optimization strategies, and implementation constraints. We then propose a reference architecture in which a quantum-inspired optimization engine sits beside a conventional OFDM/MIMO transmit-receive chain and reconfigures modulation, beam-selection and decoding parameters from channel-state feedback. An illustrative simulation grounds the discussion: a representative QISP optimizer is compared against a conventional adaptive baseline over a 4×4 MIMO, QPSK, AWGN-channel OFDM link at signal-to-noise ratios (SNR) from 0 to 20 dB. These numbers demonstrate methodology and are not measurements taken from physical hardware. Within that caveat, the QISP optimizer achieves a lower bit-error rate (BER) at low and moderate SNR, and the throughput and latency trends are consistent with the parameter-search efficiency reported in the wider literature. The paper concludes with open problems such as scalability, algorithmic complexity, explainability and standardized benchmarking, and research directions on hybrid quantum-classical processors, reconfigurable intelligent surfaces (RIS), semantic communications, and edge-native QISP inference.
Key Words: Quantum-inspired computing, signal processing, 6G wireless networks, combinatorial optimization, MIMO, OFDM, adaptive modulation, tensor networks, machine learning for communications, reconfigurable intelligent surfaces..
Citation: Miska. B., “A Study of Quantum-Inspired Signal Processing for Future Communication Systems” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 2(2), pp. 88-97, 2025. doi: 10.55306/CJDTES.2025.020202

Quantum-Dot Cellular Automata-Based Nano-Processors for Next Generation Computing: A Comprehensive Review, Design Methodologies, Performance Analysis and Future Research Directions
Author: Naveed Farhana, Humna Abdul Mumeed
Pages: 98-116
DOI: https://doi.org/10.55306/CJDTES.2025.020203
Abstract:

Complementary metal-oxide-semiconductor (CMOS) technology has driven digital electronics for more than five decades, but below the 5 nm node its returns are eroding: short-channel effects, quantum tunnelling leakage and rising power density now consume much of what further scaling delivers. Quantum-dot Cellular Automata (QCA) is among the most actively studied beyond-CMOS alternatives, encoding a bit in the charge configuration of coupled quantum dots rather than in transistor switching current. In principle this allows terahertz-range operation, switching energies far below those of scaled CMOS, and very high integration density. After roughly two decades of circuit-level work, however, QCA processing architectures remain fragmented across isolated combinational and sequential building blocks; a unified, physically consistent and quantitatively benchmarked architecture for a complete QCA nano-processor, covering arithmetic, control, memory, interconnect and clocking, is still missing from the literature. This paper consolidates the physical and mathematical foundations of QCA computation, reviews design contributions published between 2021 and 2025 across adders, multiplexers, memories and arithmetic logic units, proposes a coherent nano-processor architecture built from majority-logic primitives, and benchmarks QCA quantitatively against CMOS and competing beyond-CMOS technologies. The approach combines analytical modelling (Hamiltonian and kink-energy formulations, clocked cell-relaxation dynamics) with architectural synthesis by hierarchical decomposition into fetch/decode, ALU, register-file, memory and clocking subsystems, drawing on a comparative synthesis of fifty-three peer-reviewed sources; normalised projections for area, delay and switching energy are compiled from published simulation benchmarks rather than newly measured. Majority-logic-optimised QCA arithmetic circuits report reductions of roughly 58 to 71 per cent in normalised area-delay product relative to CMOS baselines of comparable generation, with switching energies two to four orders of magnitude below projected sub-5 nm CMOS. Reversible QCA arithmetic logic units report cell-count and area savings near 50 per cent alongside large energy-efficiency gains, though clocking-network overhead, cell-displacement defects and thermal sensitivity remain the unresolved obstacles standing between these results and large-scale integration. On this basis the paper contributes a consistent mathematical treatment of QCA cell dynamics and clocking, a modular nano-processor reference architecture, an updated comparative taxonomy of state-of-the-art QCA building blocks, and a CMOS-QCA benchmarking framework. Priority directions for future work include hybrid CMOS-QCA co-design, molecular and magnetic QCA implementations operating nearer room temperature, defect-aware automated layout synthesis, and machine-learning-assisted clocking-zone optimisation.
Key Words: Quantum-dot cellular automata; nanoelectronics; beyond-CMOS computing; majority logic gate; QCA clocking scheme; nano-processor architecture; low-power VLSI design; reversible logic; molecular QCA; emerging nanotechnology.
Citation: Farhana N et. al., “Quantum-Dot Cellular Automata-Based Nano-Processors for Next-Generation Computing: A Comprehensive Review, Design Methodologies, Performance Analysis, and Future Research Directions” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 2(2), pp. 98-116, 2025, doi: 10.55306/CJDTES.2025.020203

Design of Secure Hardware Architectures for Post-Quantum Cryptography Applications
Author: Prabhakar Rao Barre
Pages: 117-129
DOI: https://doi.org/10.55306/CJDTES.2025.020204
Abstract:

A cryptographically relevant quantum computer is no longer science fiction, and that reality has forced the standardization of post-quantum cryptographic (PQC) algorithms: the lattice-based Kyber (ML-KEM) and Dilithium (ML-DSA), the code-based Classic McEliece, and the hash-based SPHINCS+ among them. Getting these algorithms running on embedded systems, IoT nodes and hardware security modules (HSMs) requires more than porting software Post-quantum cryptography needs hardware that does it all. It needs to be fast, compact and energy-efficient, while also being a fortress against physical hacking tactics like side-channel or fault-injection attacks. To solve this problem we built a secure hardware accelerator for PQC from scratch. Its heart is a highly protected Datapath with a masked polynomial arithmetic unit, constant-time engines for both NTT and noise sampling, a Keccak/SHA-3 core, and dedicated blocks fully dedicated to hiding data and fault detection. We thoroughly validated this architecture with FPGA simulations for five top NIST-backed PQC algorithms. The standout result? Our first-order masking effectively neutralizes 96% of side-channel data leaks compared to a standard, unprotected core. The trade-offs are well worth the security gain, requiring just a 38% increase in chip footprint and a 22% bump in processing time. Push to fourth order (d=4) and leakage reduction exceeds four orders of magnitude, with overhead scaling accordingly. Throughput, resource utilization, and power trade-offs are quantified across all five schemes, along with practical guidance for picking a masking order and hiding strategy to match a given threat model and resource budget.
Key Words: Contemporary power system, Controlling reactive power, Electric networks, Flexible AC Transmission Systems, Reactive power, Real-world application, Modern power systems, Unified Power Flow Controller.
Citation: Constant-Time Implementation, Dilithium, Fault Injection, FPGA, Hardware Security, Kyber, Lattice-Based Cryptography, Masking Post-Quantum Cryptography, Side-Channel Analysis.

Explainable Transformer-Based Fault Diagnosis in Smart Grids Using Graph Attention Networks
Author: Rajani Daggumati
Pages: 130-138
DOI: https://doi.org/10.55306/CJDTES.2025.020205
Abstract:

The intelligence smart grids of power infrastructure have also augmented the complexity of the system, and thus fault diagnosis has become an essential requirement in guaranteeing reliability and stability of the system. Traditional fault detection techniques and deep learning networks are not very interpretable and do not learn spatial relationships among grid elements, which restricts their performance in real-time usage. The research gap is in the lack of a single framework combining spatial-temporal modeling and explainable decision-making, which would result in accurate fault diagnosis. To solve this, an Explainable Transformer-Based Fault Diagnosis model with Graph Attention Networks (ET-GAT) is suggested. The model integrates spatial relationship modeling based on graph attention mechanisms and temporal encoding based on transformers, as well as the causal attribution of explainability. The simulated fault conditions are used to experiment with benchmark power system datasets, such as IEEE 118-bus and real-world PMU data, experimentally. The accuracy, precision, recall, and F1-score of the model proposed are 97.58%, 96.84%, 97.12%, and 96.98%, respectively, which is superior to the existing approaches. The findings show that the fault detection has better interpretability and fault detection ability which allows reliable and clear decision making in smart grid conditions.
Key Words: Explainable AI, Fault Diagnosis, Graph Attention Networks, Power System Analytics, Smart Grids, Transformer Models.
Citation: Rajani D et al., “Explainable Transformer-Based Fault Diagnosis in Smart Grids Using Graph Attention Networks” Ci-STEM Journal of Digital Technologies and Expert Systems, Vol. 2(2), pp. 130-138, 2025. doi:10.55306/CJDTES.2025.020205